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| HEX D FLIP-FLOP SY100S351 FEATURES s s s s s s s s s s s Max. toggle frequency of 700MHz Clock to Q max. of 1200ps IEE min. of -98mA Industry standard 100K ECL levels Extended supply voltage option: VEE = -4.2V to -5.5V Voltage and temperature compensation for improved noise immunity Internal 75K input pull-down resistors 50% faster than Fairchild 300K Better than 20% lower power than Fairchild Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages DESCRIPTION The SY100S351 offers six D-type, edge-triggered, master/slave flip-flops with differential outputs, and is designed for use in high-performance ECL systems. The flip-flops are controlled by the signal from the logical OR operation on a pair of common clock signals (CPa, CPb). Data enters the master when both CPa and CPb are LOW and transfers to the slave when either CPa or CPb (or both) go to a logic HIGH. The Master Reset (MR) input overrides all other inputs and takes the Q outputs to a logic LOW. The inputs on this device have 75K pull-down resistors. PIN CONFIGURATIONS D0 Q0 VEES Q0 Q1 Q1 4 3 2 1 28 27 26 19 20 21 22 23 24 25 11 10 9 8 7 6 5 D2 D3 VEE VEES MR 12 13 14 15 16 17 18 Q2 Q2 VCCA VCC VCC Q3 Q3 D1 CPa CPb Top View PLCC J28-1 BLOCK DIAGRAM D5 CPb CPa MR D4 D E R Q Q Q5 Q5 CPb CPa MR VEE D3 D5 Q5 VEES Q5 Q4 D E R Q Q Q4 Q4 D4 D5 Q5 Q5 Q4 Q4 1 2 3 4 5 6 24 23 22 21 20 19 18 Top View Flatpack F24-1 17 16 15 14 D2 D4 Q4 D1 D0 Q0 Q0 Q1 Q1 D3 D E R Q Q Q3 Q3 13 7 8 9 10 11 12 Q3 VCC Q3 D2 D E R Q Q Q2 Q2 D1 D E Q RQ Q RQ Q1 Q1 D0 D E Q0 Q0 Rev.: G VCCA Q2 Q2 Amendment: /0 1 Issue Date: July, 1999 Micrel SY100S351 PIN NAMES Pin D0 -- D5 CPa, CPb MR Q0 -- Q5 Q0 -- Q5 VEES VCCA Data Inputs Common Clock Inputs Asynchronous Master Reset Input Data Outputs Complementary Data Outputs VEE Substrate VCCO for ECL Outputs Function TRUTH TABLES Asynchronous Operation(1) Inputs Dn X CPa X CPb X MR H Outputs Qn (t+1) L Dn L H L H X X X CPa u u L L H u L Synchronous Operation(1) Inputs CPb L L u u u H L MR L L L L L L L Outputs Qn (t+1) L H L H Qn(t) Qn(t) Qn(t) NOTE: 1. H = High Voltage Level L = Low Voltage Level X = Don't Care t = Time before CP Positive Transition t+1 = Time after CP Positive Transition u = LOW-to-HIGH Transition DC ELECTRICAL CHARACTERISTICS VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND Symbol IIH Parameter Input HIGH Current MR D0 - D5 CPa, CPb Power Supply Current Min. -- -- -- -98 Typ. -- -- -- -71 Max. 270 200 300 -49 mA Inputs Open Unit A Condition VIN = VIH (Max.) IEE 2 Micrel SY100S351 AC ELECTRICAL CHARACTERISTICS CERPACK VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND TA = 0C Symbol fMAX tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Toggle Frequency Propagation Delay CPa, CPb to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Set-up Time D0-D5 MR (Release Time) Hold Time, D0-D5 Pulse Width HIGH CPa, CPb, MR Min. 700 -- -- 300 Max. -- 1200 1200 900 TA = +25C Min. 700 -- -- 300 Max. -- 1200 1200 900 TA = +85C Min. 700 -- -- 300 Max. -- 1200 1200 900 Unit MHz ps ps ps ps 500 1000 550 1000 -- -- -- -- 500 1000 550 1000 -- -- -- -- 500 1000 550 1000 -- -- -- -- ps ps Condition tH tPW (H) PLCC VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND TA = 0C Symbol fMAX tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Toggle Frequency Propagation Delay CPa, CPb to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Set-up Time D0-D5 MR (Release Time) Hold Time, D0-D5 Pulse Width HIGH CPa, CPb, MR Min. 700 -- -- 300 Max. -- 1200 1200 900 TA = +25C Min. 700 -- -- 300 Max. -- 1200 1200 900 TA = +85C Min. 700 -- -- 300 Max. -- 1200 1200 900 Unit MHz ps ps ps ps 500 1000 550 1000 -- -- -- -- 500 1000 550 1000 -- -- -- -- 500 1000 550 1000 -- -- -- -- ps ps Condition tH tPW (H) 3 Micrel SY100S351 TIMING DIAGRAMS DATA 0.7 0.1 ns 0.7 0.1 ns -0.95V 80% 50% 20% -1.69V CLOCK 1/fmax tPHL tPLH tpw (H) OUTPUT 50% tPLH tPHL OUTPUT tTLH tTHL Propagation Delay (Clock) and Transition Times NOTE: VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND 0.7 0.1 ns 0.7 0.1 ns -0.95V 80% 50% 20% -1.69V tS (RELEASE TIME) tpw (H) MR CLOCK 50% tPHL tPLH OUTPUT 50% tPLH tPHL 80% 50% 20% OUTPUT Propagation Delay (Resets) 4 Micrel SY100S351 TIMING DIAGRAMS -0.95V DATA 50% -1.69V tH tS -0.95V CLOCK 50% -1.69V Data Set-up and Hold Time NOTES: 1. VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND 2. tS is the minimum time before the transition of the clock that information must be present at the data input. 3. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. PRODUCT ORDERING CODE Ordering Code SY100S351FC SY100S351JC SY100S351JCTR Package Type F24-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial 5 Micrel SY100S351 24 LEAD CERPACK (F24-1) Rev. 03 6 Micrel SY100S351 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 7 |
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